The present invention relates to a semiconductor device having a transistor circuit with a Darlington structure and, more particularly, to a Darlington transistor circuit in which a p-n junction diode, for obtaining a high speed switching characteristic, is added between the base and collector, and which is particularly used for a switching transistor and a power transistor module product.
A Darlington transistor circuit, which is obtained by cascade-connecting a plurality of transistors, has a very high total current-amplification factor, because the total current-amplification factor is a product of current-amplification factors of respective transistors. When this transistor circuit is used as a switching element for switching a large current, a so-called drive current is reduced very much, so that the Darlington transistor circuit is suitable as a high power transistor. In this case, the high-speed switching characteristic of the Darlington transistor circuit is an important factor for a switching device. Although the switching time of a transistor is determined by various factors, switching-off time (turn-off time) t.sub.off, consisting of the sum of storage time t.sub.stg (a time interval between the end of input pulse and the beginning of change in output pulse) and fall time t.sub.f (a time interval between the beginning and end of change in output pulse) is important. In order to reduce t.sub.off, the amount of extra minority carriers stored in base and collector regions during an ON state must be set to be a proper value required for maintaining the ON state, and must be rapidly dissipated upon turning off the transistor.
As a conventional technique for obtaining a high-speed characteristic in the transistor, a method of diffusing a carrier lifetime killer such as gold, platinum, or the like into the base region of a semiconductor chip, or performing electron beam irradiation to reduce the lifetime of the carriers at the region, is widely used. However, according to these methods, since the carrier lifetime in the base region is reduced, the linearity of DC current-amplification factor h.sub.FE vs. collector current I.sub.C is degraded, or collector-emitter saturation voltage V.sub.CE (sat) is increased. (Note that in the case of the h.sub.FE vs. I.sub.C characteristic, reducing the maximum peak value of h.sub.FE without reducing h.sub.FE at a switching point, i.e., maintaining h.sub.FE constant with respect to changes in I.sub.C, improves the linearity of h.sub.FE. This allows a reduction in turn-off time t.sub.off.) For this reason, a large chip size is required to obtain predetermined characteristics in consideration of linearity-degradation of h.sub.FE. This results in high manufacturing cost and large variations in chip characteristics.
Conventional module products will now be described below.
FIG. 1 shows an equivalent circuit diagram of a high-power module product of a three-stage Darlington transistor circuit. In order to reduce switching-off time t.sub.off, diode D.sub.a is connected between input terminal B and collector terminal C, and cross-coupled diodes D.sub.b and D.sub.c are connected between input terminal B and base terminal B1 of first-stage transistor TR1. With this arrangement, a forward bias voltage of input terminal B and emitter terminal E1 of the first-stage transistor (having the same potential as that of base terminal B2 of the next-stage transistor) can be increased more than a forward bias voltage of diode D.sub.a connected between terminals B and C. Therefore, since part of the base current flowing from terminal B during the ON state of transistor TR1 is bypassed to diode D.sub.a, a current flowing into base terminal B1 of transistor TR1 is reduced, so that oversaturation of transistors TR1-TR3 can be prevented, thereby reducing t.sub.off.
However, in this method, collector-emitter saturation voltage V.sub.CE (sat) of transistor TR3 is increased by an amount corresponding to a forward built-in voltage (about 0.6 V) of diode D.sub.b inserted between terminals B and B1, resulting in increased power loss of the Darlington transistor circuit upon mounting in an actual circuit. On the other hand, in a semiconductor device manufacturing process, an additional three diode chips are required, and strict characteristic control is required for cross-coupled diodes D.sub.b and D.sub.c. In addition, the number of assembly steps such as chip mounting or chip bonding increases as the number of chips increases, resulting in high manufacturing cost. Reduction in power loss, obtained by improvement of switching characteristic, is cancelled by the increase in power loss caused by an increase in V.sub.CE(sat) ), so that practical advantages, justifying the high manufacturing cost, cannot be obtained.
Recently, in switching semiconductor devices, (a) high withstand voltage, (b) high current gain, and (c) high speed are strong requirements in the market place, but, in relation to semiconductor design, these three characteristics are mutually contradictory. Therefore, products manufactured by conventional techniques cannot satisfy the above-mentioned requirements. For example, when the lifetime of minority carriers in the base is reduced to improve t.sub.off, as described above, characteristics of h.sub.FE, such as linearity, are degraded. Further, even if an additional three diodes are used as in the module circuit of FIG. 1, to reduce t.sub.off, problems such as an increase in V.sub.CE (sat) and high manufacturing cost are posed.